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general description the MAX5312 12-bit, serial-interface, digital-to-analog converter (dac) provides bipolar ?v to ?0v outputs from ?2v to ?5v power-supply voltages, or a unipo- lar 5v to 10v output from a single 12v to 15v power- supply voltage. the MAX5312 features excellent linearity with both inte- gral nonlinearity (inl) and differential nonlinearity (dnl) guaranteed to ? lsb (max). the device also features a fast 10? to 0.5 lsb settling time, and a hardware- shutdown feature that reduces current consumption to 3.5?. the output goes to midscale at power-up in bipolar mode (0v), and to zero scale at power-up in unipolar mode (0v). a clear input ( clr ) asynchronously clears the dac register and sets the output to 0v. the output can be asynchronously updated with the load dac ( ldac ) input. the device features a 10mhz spi-/qspi-/ microwire-compatible serial interface that oper- ates with 3v or 5v logic. additional features include a serial-data output (dout) for daisy chaining and read- back functions. the MAX5312 requires a 2v to 5.25v external reference voltage and is available in a 16-pin ssop package that operates over the extended -40 c to +85 c temperature range. applications motor control industrial process controls industrial automation automatic test equipment (ate) analog i/o boards data-acquisition systems features ? unipolar or bipolar output-voltage ranges unipolar: 0 to (+2 x v ref ) (single or dual supply) bipolar: (-2 x v ref ) to (+2 x v ref ) (dual supply) ? guaranteed inl 1 lsb (max) ? guaranteed monotonic: dnl 1 lsb (max) ? 10s settling time to 0.5 lsb ? low 3.5a shutdown current ? 10mhz spi-/qspi-/microwire-compatible serial interface ? power-on reset sets dac output to 0v ? schmitt trigger inputs for direct optocoupler interface ? serial-data output allows daisy chaining of devices ? small 16-pin ssop MAX5312 10v, 12-bit, serial, voltage-output dac ________________________________________________________________ maxim integrated products 1 ordering information 19-3119; rev 0; 12/03 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. part temp range pin-package MAX5312eae -40 c to +85 c 16 ssop 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 sclk v dd ref v ss agnd sgnd out top view MAX5312 ssop din v cc dout dgnd cs shdn uni/bip ldac clr pin configuration spi and qspi are trademarks of motorola, inc. microwire is a trademark of national semiconductor corp.
MAX5312 10v, 12-bit, serial, voltage-output dac 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (dual supply) (v dd = +15v ?%, v ss = -15v ?%, v cc = +5v ?0%, agnd = dgnd = sgnd = 0v, v ref = 5v, r load = 2k ? , c load = 250pf, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v dd to agnd..........................................................-0.3v to +17v v ss to agnd ..........................................................-17v to +0.3v v dd to v ss ..........................................................................+34v v cc to dgnd ...........................................................-0.3v to +6v agnd to dgnd.....................................................-0.3v to +0.3v sgnd to agnd .....................................................-0.3v to +0.3v sclk, din, cs , shdn , uni/ bip , clr , ldac , dout to dgnd ..........................-0.3v to (v cc + 0.3v) out to agnd ..................................(v ss - 0.3v) to (v dd + 0.3v) ref to agnd............................................................-0.3v to +6v maximum current into ref...............................................?0ma maximum current into any pin excluding ref.................?0ma continuous power dissipation (t a = +70?) 16-pin ssop (derate 7.1mw/? above +70?) ...........571mw operating temperature range ...........................-40? to +85? junction temperature ......................................................+150? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? parameter symbol conditions min typ max units static accuracy resolution n 12 bits integral nonlinearity inl 1 lsb differential nonlinearity dnl guaranteed monotonic 1 lsb bipolar, code = 800hex 1 zero-scale error unipolar, code = 000hex 2 lsb bipolar 0.3 zero-scale temperature coefficient unipolar 0.5 ppm fsr/ c bipolar, no load 2 gain error unipolar, no load 2 lsb bipolar, no load 2 gain-error temperature coefficient unipolar, no load 2 ppm fsr/ c analog output (out) output voltage range (v ss + 1.5v) < v out < (v dd - 1.5v) -2 x v ref +2 x v ref v resistive load to gnd r load 2k ? capacitive load to gnd c load 250 pf dc output resistance 0.5 ? sgnd input (sgnd) input impedance 92 k ? reference input (ref) reference-voltage input range 2.00 5.25 v code = 555hex, worst-case code 15 22 input resistance r ref shutdown 22 k ? reference bandwidth v ref = 200mv p-p + 5vdc 200 khz
MAX5312 10v, 12-bit, serial, voltage-output dac _______________________________________________________________________________________ 3 parameter symbol conditions min typ max units digital inputs (sclk, din, cs , shdn , uni/ bip , clr , ldac ) +2.7v v cc +3.6v 0.7 x v cc input-voltage high v ih +4.5v v cc +5.5v 2.4 v +2.7v v cc +3.6v 0.6 input-voltage low v il +4.5v v cc +5.5v 0.8 v +2.7v v cc +3.6v 10 input capacitance c +4.5v v cc +5.5v 10 pf 0 all digital inputs v cc , +2.7v v cc +3.6v ? input current (note 1) 0 all digital inputs v cc , +4.5v v cc +5.5v ? ? digital output (dout) output-voltage high v oh i source = 2ma v cc - 0.5 v output-voltage low v ol i sink = 2ma 0.4 v tri-state leakage current 0.2 ? tri-state capacitance 10 pf dynamic performance voltage-output slew rate 2.5 v/? output settling time to 0.5 lsb of full scale, code 000 to code fff 10 ? digital feedthrough cs = high, f sclk = 10mhz, v out = 0v 10 nv-s output-noise spectral density at 10khz 130 nv/ hz power supplies positive analog-supply voltage v dd 10.80 15.75 v negative analog-supply voltage v ss -10.80 -15.75 v positive digital-supply voltage v cc 2.7 5.5 v positive analog-supply current i dd output unloaded, v out = fs 1.8 4ma negative analog-supply current i ss output unloaded, v out = fs 0.75 -2 ma digital-supply current i cc all digital inputs = 0 or v cc 30 200 ? positive analog supply 0.4 power-supply rejection ratio (note 2) psrr negative analog supply 0.6 lsb/v positive analog supply 1.7 50 negative analog supply 2.4 50 shutdown current digital supply 3.5 10 ? electrical characteristics (dual supply) (continued) (v dd = +15v ?%, v ss = -15v ?%, v cc = +5v ?0%, agnd = dgnd = sgnd = 0v, v ref = 5v, r load = 2k ? , c load = 250pf, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c.)
MAX5312 10v, 12-bit, serial, voltage-output dac 4 _______________________________________________________________________________________ electrical characteristics (single supply) (v dd = +15v ?%, v ss = 0v, v cc = +5v ?0%, agnd = dgnd = sgnd = 0v, v ref = 5v, r load = 10k ? , c load = 250pf, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c.) parameter symbol conditions min typ max units static accuracy resolution n 12 bits integral nonlinearity inl (note 3) 1 lsb differential nonlinearity dnl guaranteed monotonic 1 lsb unipolar zero-scale error code = 14hex 2 lsb unipolar zero-scale temperature coefficient code = 14hex 0.05 ppm fsr/ c gain error no load 2 lsb gain-error temperature coefficient no load 2 ppm fsr/ c analog output (out) output voltage range 0 +2 x v ref v resistive load to gnd r load 10 k ? capacitive load to gnd c load 250 pf dc output resistance 0.5 ? sgnd input (sgnd) input impedance 92 k ? reference input (ref) reference-voltage input range 2.00 5.25 v input resistance code = 555hex, worst-case code 15 22 k ? reference input bandwidth v ref = 200mv p-p + 5v dc 150 khz digital inputs (sclk, din, cs , shdn , uni/ bip , clr , ldac ) +2.7v v cc +3.6v 0.7 x v cc input-voltage high v ih +4.5v v cc +5.5v 2.4 v +2.7v v cc +3.6v 0.6 input-voltage low v il +4.5v v cc +5.5v 0.8 v +2.7v v cc +3.6v 10 input capacitance c in +4.5v v cc +5.6v 10 pf 0 v in v cc, +2.7v v cc +3.6v ? input current i in 0 v in v cc, +4.5v v cc +5.5v ? ? digital output (dout) output-voltage high v oh i source = 2ma v cc - 0.5 v output-voltage low v ol i sink = 2ma 0.4 v tri-state leakage current 0.2 ?
MAX5312 10v, 12-bit, serial, voltage-output dac _______________________________________________________________________________________ 5 electrical characteristics (single supply) (continued) (v dd = +15v ?%, v ss = 0v, v cc = +5v ?0%, agnd = dgnd = sgnd = 0v, v ref = 5v, r load = 10k ? , c load = 250pf, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c.) parameter symbol conditions min typ max units tri-state capacitance 10 pf dynamic performance voltage-output slew rate 2.5 v/? output settling time to 0.5 lsb of full scale, code 14hex to code fff 10 ? digital feedthrough cs = high, f sclk = 10mhz, v out = 0v 10 nv-s output-noise spectral density at 1khz 130 nv/ hz power supplies positive analog-supply voltage v dd 10.80 15.75 v negative analog-supply voltage v ss 0v positive digital-supply voltage v cc 2.7 5.5 v positive analog-supply current i dd output unloaded, v out = 0 1.8 4 ma negative analog-supply current i ss output unloaded, v out = 0 0.75 -2 ma digital-supply current i cc all digital inputs = 0 or v cc 30 200 ? power-supply rejection ratio psrr ? v dd = 14.5v to 15.5v, code fff 0.04 lsb/v analog supply 1.7 50 shutdown current digital supply 3.5 10 ?
MAX5312 10v, 12-bit, serial, voltage-output dac 6 _______________________________________________________________________________________ timing characteristics (v dd = +15v, v ss = -15v or 0v, v cc = +2.7v to +5.5v, agnd = dgnd = sgnd = 0, v ref = 5v, r load = 2k ? , c load = 250pf, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c.) parameter symbol conditions min typ max units sclk frequency 10 mhz sclk clock period t cp 100 ns sclk pulse-width high t ch for nondaisy-chain use 45 ns sclk pulse-width low t cl for nondaisy-chain use 45 ns cs fall to sclk rise setup time t css 40 ns +2.7v v cc +3.6v 15 sclk rise to cs rise hold time t csh +4.5v v cc +5.5v 10 ns din setup time t ds 20 ns din hold time t dh 10 ns ldac pulse width t ld 50 ns +2.7v v cc +3.6v 100 cs rise to ldac low setup time t lds +4.5v v cc +5.5v 50 ns c load = 20pf, +2.7v v cc +3.6v 100 sclk fall to dout valid propagation delay t do1 c load = 20pf, +4.5v v cc +5.5v 80 ns sclk rise to cs fall delay t cs0 10 ns cs low to dout valid time t cse c load = 20pf 120 ns cs high to dout disabled time t csd 120 ns cs rise to sclk rise hold time t cs1 50 ns +2.7v v cc +3.6v 200 cs pulse-width high t csw +4.5v v cc +5.5v 100 ns clr pulse-width low t clr 50 ns note 1: output unloaded, digital inputs = v cc or dgnd. note 2: ? v dd = +14.5v to +15.5v, ? v ss = -15.5v to -14.5v, code = fff. note 3: measured from code 14hex to fffhex.
MAX5312 10v, 12-bit, serial, voltage-output dac _______________________________________________________________________________________ 7 intergral nonlinearity vs. input code MAX5312 toc01 input code (decimal) inl (lsb) 3072 2048 1024 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 -0.5 0 4096 integral nonlinearity vs. reference voltage MAX5312 toc02 v ref (v) inl (lsb) 5.0 4.5 2.5 3.0 3.5 4.0 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.10 2.0 5.5 differential nonlinearity vs. input code MAX5312 toc03 input code (decimal) dnl (lsb) 3072 2048 1024 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 -0.5 0 4096 differential nonlinearity vs. reference voltage MAX5312 toc04 v ref (v) dnl (lsb) 5.0 4.5 2.5 3.0 3.5 4.0 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.10 2.0 5.5 integral nonlinearity vs. temperature MAX5312 toc05 temperature ( c) inl (lsb) 60 35 10 -15 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 -40 85 differential nonlinearity vs. temperature (worst-case codes) MAX5312 toc06 temperature ( c) dnl (lsb) 60 35 10 -15 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 -40 85 code = 9ffhex code = 7ffhex unipolar settling time (c load = 250pf, r load = 2k ? ) MAX5312 toc07 t = 10.0 s/div 5v/div 2v/div 0 cs v out bipolar settling time (c load = 250pf, r load = 10k ? ) MAX5312 toc08 t = 10.0 s/div 5v/div 5v/div 0 cs v out bipolar major carry glitch energy, c load = 250pf MAX5312 toc09 t = 4.00 s/div 5v/div 100mv/div cs v out t ypical operating characteristics (v dd = +15v, v ss = -15v for bipolar graphs, v ss = 0 for unipolar graphs, v cc = +5v, agnd = dgnd = sgnd = 0, v ref = +5.0v, output unloaded, t a = +25 c, all graphs apply to both unipolar and bipolar, unless otherwise noted.)
bipolar positive supply current vs. supply voltage MAX5312 toc17 v dd (v) i dd (ma) 14.78 13.76 11.72 12.74 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 10.70 15.80 v ss = -15v MAX5312 10v, 12-bit, serial, voltage-output dac 8 _______________________________________________________________________________________ bipolar major carry glitch c load = 10pf MAX5312 toc10 t = 4.00 s/div 5v/div 100mv/div cs v out unipolar zero-scale voltage vs. temperature MAX5312 toc11 temperature ( c) v out (mv) 60 35 -15 10 43 44 45 46 47 48 49 50 42 -40 85 code = 014hex bipolar midscale voltage vs. temperature MAX5312 toc12 temperature ( c) v out (mv) 60 35 10 -15 0.5 1.0 1.5 2.0 2.5 0 -40 85 code = 800hex unipolar full-scale voltage vs. temperature MAX5312 toc13 temperature ( c) v out (mv) 60 35 10 -15 9.995 9.996 9.997 9.998 9.999 10.000 9.994 -40 85 code = fffhex bipolar positive full-scale voltage vs. temperature MAX5312 toc14 temperature ( c) v out (mv) 60 35 10 -15 9.995 9.996 9.997 9.998 9.994 9.993 9.992 -40 85 code = fffhex bipolar negative full-scale voltage vs. temperature MAX5312 toc15 temperature ( c) v out (mv) 60 35 10 -15 -9.995 -9.996 -9.997 -9.998 -9.994 -9.993 -9.992 -40 85 code = 000hex unipolar supply current vs. supply voltage MAX5312 toc16 v dd (v) i dd (ma) 14.78 13.76 11.72 12.74 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 10.70 15.80 v ss = 0v t ypical operating characteristics (continued) (v dd = +15v, v ss = -15v for bipolar graphs, v ss = 0 for unipolar graphs, v cc = +5v, agnd = dgnd = sgnd = 0, v ref = +5.0v, output unloaded, t a = +25 c, all graphs apply to both unipolar and bipolar, unless otherwise noted.)
MAX5312 10v, 12-bit, serial, voltage-output dac _______________________________________________________________________________________ 9 bipolar negative supply current vs. supply voltage MAX5312 toc18 v ss (v) i ss (ma) -14.78 -13.76 -11.72 -12.74 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 -4.0 0 -10.70 -15.80 v dd = 15v unipolar supply current vs. temperature MAX5312 toc19 temperature ( c) i dd (ma) 60 35 10 -15 0.5 1.0 1.5 2.0 2.5 3.0 0 -40 85 v ss = 0v bipolar positive supply current vs. temperature MAX5312 toc20a temperature ( c) i dd (ma) 60 35 10 -15 1.8 1.9 2.0 2.1 2.2 1.7 -40 85 bipolar negative supply current vs. temperature MAX5312 toc20b temperature ( c) i ss (ma) 60 35 10 -15 -0.90 -0.85 -0.80 -0.75 -0.70 -0.65 -0.60 -0.55 -0.50 -0.45 -0.95 -40 85 unipolar shutdown current vs. temperature MAX5312 toc21 temperature ( c) shutdown current ( a) 60 35 10 -15 0 1 2 3 4 5 -1 -40 85 i cc i ss i dd bipolar shutdown current vs. temperature MAX5312 toc22 temperature ( c) shutdown current ( a) 60 35 -15 10 -3 -2 -1 0 2 1 3 4 -4 -40 85 i cc i ss i dd unipolar output voltage vs. output current MAX5312 toc23a i out (ma) v out (v) 16 12 8 4 9.965 9.970 9.975 9.980 9.985 9.990 9.995 10.000 10.005 9.960 020 code = fffhex unipolar output voltage vs. output current MAX5312 toc23b i out (ma) v out (v) 1.0 0.8 0.6 0.4 0.2 0.055 0.065 0.075 0.085 0.095 0.105 0.115 0.125 0.135 0.045 01.2 code = 014hex t ypical operating characteristics (continued) (v dd = +15v, v ss = -15v for bipolar graphs, v ss = 0 for unipolar graphs, v cc = +5v, agnd = dgnd = sgnd = 0, v ref = +5.0v, output unloaded, t a = +25 c, all graphs apply to both unipolar and bipolar, unless otherwise noted.)
MAX5312 10v, 12-bit, serial, voltage-output dac 10 ______________________________________________________________________________________ bipolar output voltage vs. output current MAX5312 toc24b i out (ma) v out (v) 16 12 48 10.000 9.995 9.990 9.985 9.980 9.975 9.970 9.960 9.965 10.005 020 code = fffhex bipolar ref input resistance vs. input code MAX5312 toc26 input code (decimal) ref input resistance (m ? ) 3072 2048 1024 0.1 1 10 100 0.01 0 4096 unipolar reference input bandwidth MAX5312 toc27 frequency (khz) response (db) 100 10 1 0.1 -12 -9 -6 -3 0 3 6 -15 0.01 1000 ref = 0.2v p-p + 5.0vdc bipolar reference input bandwidth MAX5312 toc28 frequency (khz) response (db) 100 10 1 0.1 -12 -9 -6 -3 0 3 6 -15 0.01 1000 ref = 0.2v p-p + 5.0vdc unipolar startup response, c load = 10pf MAX5312 toc29a t = 10.0 s/div v dd 20v/div 5v/div 5v/div 2v/div v cc v ref v out unipolar startup response, c load = 250pf MAX5312 toc29b t = 10.0 s/div v dd v cc v ref v out 20v/div 5v/div 5v/div 1v/div t ypical operating characteristics (continued) (v dd = +15v, v ss = -15v for bipolar graphs, v ss = 0 for unipolar graphs, v cc = +5v, agnd = dgnd = sgnd = 0, v ref = +5.0v, output unloaded, t a = +25 c, all graphs apply to both unipolar and bipolar, unless otherwise noted.) bipolar output voltage vs. output current MAX5312 toc24a i out (ma) v out (v) -4 -8 -16 -12 -10.000 -9.995 -9.990 -9.985 -9.980 -9.975 -9.970 -9.965 -10.005 -20 0 code = 000hex 0 3072 1024 2048 4096 unipolar ref input resistance vs. input code MAX5312 toc25 input code (decimal) 0.01 0.1 1 ref input resistance (m ? )
MAX5312 10v, 12-bit, serial, voltage-output dac ______________________________________________________________________________________ 11 MAX5312 toc31 v out unipolar release from hardware-shutdown response v shdn t = 100 s/div 5v/div 2v/div MAX5312 toc32 v out bipolar release from hardware-shutdown response v shdn t = 100 s/div 5v/div 2v/div MAX5312 toc33a v out unipolar software-shutdown response cs t = 40.0 s/div 5v/div 5v/div MAX5312 toc33b v out bipolar software-shutdown response cs t = 40.0 s/div 5v/div 10v/div bipolar startup response, c load = 10pf MAX5312 toc30a v dd v cc v ss v out t = 10.0 s/div 20v/div 5v/div 10v/div 2v/div bipolar startup response, c load = 250pf MAX5312 toc30b v dd v cc v ss v out t = 10.0 s/div 20v/div 5v/div 10v/div 1v/div t ypical operating characteristics (continued) (v dd = +15v, v ss = -15v for bipolar graphs, v ss = 0 for unipolar graphs, v cc = +5v, agnd = dgnd = sgnd = 0, v ref = +5.0v, output unloaded, t a = +25 c, all graphs apply to both unipolar and bipolar, unless otherwise noted.)
MAX5312 10v, 12-bit, serial, voltage-output dac 12 ______________________________________________________________________________________ pin name function 1 sclk serial-clock input. data is shifted from din into the internal register on the rising edge of sclk. data is clocked out at dout on the falling edge of sclk. sclk is active only while cs is low. 2dins er i al - d ata inp ut. d in i s the d ata i np ut p or t for the ser i al i nter face. c l ock d ata i n on the r i si ng ed g e of s c lk. 3 cs acti ve- low c hi p - s el ect inp ut. cs acti vates the ser i al i nter face. d r i ve cs l ow to i ni ti ate ser i al com m uni cati on. 4 dout serial-data output. dout is the data output port for the serial interface. data shifted into din appears at dout 16.5 clock cycles later, valid on the falling edge of sclk. dout is high impedance when cs is high. 5 dgnd digital ground 6v cc digital power input. v cc ranges from +2.7v to +5.5v. bypass v cc with a 0.1? and 1.0? capacitor to 7 shdn active-low shutdown input. shdn places the device into low-power shutdown mode. when shut down ref and dout are high impedance, drive shdn low to place the device into shutdown mode. 8 uni/ bip unipolar/bipolar-select input. uni/ bip selects unipolar or bipolar output. in unipolar mode, the analog output range is 0 to (+2 x v ref ). in bipolar mode, the analog output range is (-2 x v ref ) to (+2 x v ref ). drive uni/ bip high for unipolar output. drive uni/ bip low for bipolar output. dual supplies are required for bipolar operation. 9 out analog output. out is the output port for the dac. read out relative to sgnd. 10 sgnd signal ground. sgnd is the ground-reference node for the output amplifier? internal feedback resistors. connect sgnd directly to agnd. (see figure 1.) 11 agnd analog ground. agnd is the ground return for v dd and v ss . 12 v ss negative power input. bypass v ss with a 0.1? and 1.0? capacitor to agnd. if operating with a single supply, connect v ss to agnd. 13 ref external reference input. apply an external reference voltage of +2v to +5.25v to ref to determine the output voltage range. in unipolar mode, the output range is from 0 to (+2 x v ref ). in bipolar mode, the output range is from (-2 x v ref ) to (+2 x v ref ). 14 v dd positive power input. bypass v dd with a 0.1? and 1.0? capacitor to agnd. 15 clr active-low clear input. clr clears input and dac registers and resets the dac output to 0v. drive clr low to assert the clear condition. 16 ldac active-low load input. use ldac to update the dac register. ldac is an asynchronous control input. drive low to force an update. pin description
detailed description the MAX5312 12-bit dac operates from either single or dual supplies. dual ?2v to ?5v power supplies pro- vide a bipolar ?v to ?0v output, or a unipolar 0 to 10v output. single 12v to 15v power supplies provide only a unipolar 0 to 10v output. the reference input accepts voltages from 2v to 5.25v. the dac features inl and dnl less than ? lsb (max), a fast 10? settling time, and a hardware-shutdown mode that reduces current consumption to 3.5? (max). the device features a 10mhz spi-/qspi-/microwire-compatible serial inter- face that operates with 3v or 5v logic, an asynchronous load input, and a serial-data output. the device offers a clr that sets the dac output to 0v. figure 1 shows the functional diagram of the MAX5312. serial interface an spi-/qspi-/microwire-compatible serial interface allows complete control of the dac through a 16-bit control word. the first 4 bits form the control bits that determine register loading and software-shutdown functions. the last 12 bits form the dac data. the 16- bit word is entered msb first. table 1 shows the serial-data format. table 2 shows the interface commands. the MAX5312 can be programmed while in shutdown. the serial interface contains three registers: a 16-bit shift register, a 12-bit input register, and a 12-bit dac register (figure 1). the shift register accepts data from the serial interface. the input register acts as a holding register for data going to the dac register and isolates the shift reg- ister from the dac register. the dac register controls the dac ladder and thus the output voltage. any update in the dac register updates the output voltage. MAX5312 10v, 12-bit, serial, voltage-output dac ______________________________________________________________________________________ 13 v ss v cc out dout dgnd sgnd v dd din sclk ref agnd serial interface and control 2r 2r 2r 2r input register dac register 12-bit dac a1 a2 sw1 sw2 sw3 16-bit shift register 12 12 12 ldac clr cs uni/bip shdn MAX5312 figure 1. functional diagram
MAX5312 data in the shift register is transferred to the input register during the appropriate software command only. data in the input register is transferred to the dac register in one of two ways: using the software command, or through external logic control using the asynchronous load input ( ldac ). table 2 shows the software commands that transfer the data from the shift register to the input and/or dac registers. the clr , an external logic control, asyn- chronously forces the input and dac registers to zero code, and the output to 0v, in both unipolar and bipolar modes. the interface timing is shown in figures 2 and 3. wait a minimum of 100ns after cs goes high before implementing ldac or clr . if either of these logic inputs activates during a data transfer, the incoming data is corrupted and needs to be reloaded. for soft- ware control only, connect ldac and clr high. dac architecture the MAX5312 uses an inverted dac ladder architec- ture to convert the digital input into an analog output voltage. the digital input controls weighted-switches that connect the dac ladder nodes to either ref or gnd (figure 4). the sum of the weights produces the analog equivalent of the digital-input word and is then buffered at the output. 10v, 12-bit, serial, voltage-output dac 14 ______________________________________________________________________________________ control bits data bits msb lsb c3 c2 c1 c0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 table 1. serial-data format control bits* input data c3 c2 c1 c0 d11?0 function 000 0 xxxxxxxxxxxx no operation; command is ignored. 001 0 12-bit dac data load input register from shift register; dac output unchanged. 010 0 12-bit dac data load input and dac registers from shift register; dac output updated. 011 0 xxxxxxxxxxxx load d ac r eg i ster fr om i np ut r eg i ster ; d ac outp ut up d ated ; i np ut r eg i ster unchang ed . 100 0 xxxxxxxxxxxx enter shutdown; input and dac registers unchanged. 110 0 xxxxxxxxxxxx exit shutdown; input and dac registers unchanged. table 2. serial-interface programming commands x = don? care. * all unlisted commands are reserved commands. do not use. sclk din command executed 9 816 (1) 1 c2 c3 d0 c1 c0 d11 d10 d9 d6 d5 d4 d3 d2 d1 d8 d7 cs figure 2. serial-interface signals
MAX5312 10v, 12-bit, serial, voltage-output dac ______________________________________________________________________________________ 15 sclk din dout t cs0 t css t cp t csh t cs1 t csw t csd t lds t ld t ch t ds t cse t do1 t dh t cl msb lsb cs ldac figure 3. serial-interface timing diagram rrr 2r 2r 2r 2r 2r d0 d11 d10 d1 ref agnd 0 10 10 10 1 out control logic 2r 2r 2r 2r sgnd dac register sw1 sw2 sw3 MAX5312 uni/bip figure 4. basic inverted dac ladder
MAX5312 10v, 12-bit, serial, voltage-output dac 16 ______________________________________________________________________________________ external reference and transfer functions connect an external 2v to 5.25v reference to ref (the max6350 is recommended). set the output voltage range with the reference and the input code by using the equations below. unipolar output voltage: where bipolar output voltage: where where v out_uni is the unipolar output voltage, v out_bip is the bipolar output voltage, lsb uni is the unipolar lsb step size, lsb bip is the bipolar lsb step size, v ref is the reference voltage, and code is the decimal equiva- lent of the binary, 12-bit, dac input code. in either case, a 000hex input code produces the mini- mum output (-2 x v ref for bipolar and 0 for unipolar), an 800hex input code produces the midscale output (0 for bipolar and v ref for unipolar), and a fffhex input code produces the full-scale output (2 x v ref for bipo- lar and unipolar). output amplifiers the output-amplifier section can be configured as either unipolar or bipolar by the uni/ bip logic input. with uni/ bip forced low, sw1 and sw2 in figure 4 are closed, and sw3 is open. this configuration channels the dac output through two output stages to generate the ? x v ref output swing. the first amplifier gener- ates the ? ref voltage range and the second amplifier increases it by two. when configured for bipolar opera- tion, the MAX5312 must be driven with dual ?2v to ?5v power supplies. with uni/ bip forced high, switches sw1 and sw2 are open, and sw3 is closed. this configuration channels the dac output through only a single gain stage to gen- erate a 0 to (2 x v ref ) output swing. daisy chaining spi-/qspi-/microwire-compatible devices can be daisy chained to reduce i/o lines from the host con- troller (figure 7). daisy chain devices by connecting the dout of one device to the din of the next, and connect the sclk of all devices to a common clock. data is shifted out of dout 16.5 clock cycles after it is shifted into din, and is available on the rising edge of the 17th clock cycle. the spi-/qspi-/microwire-com- patible serial interface normally works at up to 10mhz, but must be slowed to 6.0mhz if daisy chaining. dout is high impedance when cs is high. shutdown shutdown is controlled by software commands or by the shdn logic input. the shdn logic input can be imple- mented at any time. the spi-/qspi-/microwire-compat- ible serial interface remains fully functional, and the device is programmable while shut down. when shut down, the MAX5312 supply current reduces to 3.5?, dout is high impedance, and out is pulled to sgnd through the inter- nal feedback resistors of the output amplifier (figure 1). when coming out of shutdown, or during device power- up, allow 350? for the output to stabilize. lsb v bip ref = 4 2 12 v lsb code v out bip bip ref _ ( )( ) = ? 2 lsb v uni ref = 2 2 12 v lsb code out uni uni _ = binary dac code analog output msb lsb unipolar (uni/ bip _ = high) bipolar (uni/ bip _ = low) 1111 1111 1111 +2 x v ref (4095 / 4096) +2 x v ref (2047 / 2048) 1000 0000 0001 +2 x v ref (2049 / 4096) +2 x v ref (1 / 2048) 1000 0000 0000 +2 x v ref (2048 / 4096) = v ref 0 0111 1111 1111 +2 x v ref (2047 / 4096) -2 x v ref (1 / 2048) 0000 0000 0001 +2 x v ref (1 / 4096) -2 x v ref (2047 / 2048) 0000 0000 0000 0 -2 x v ref (2048 / 2048) = -2 x v ref table 3. output voltage as input code examples
applications information power supplies a single +12v to +15v supply is required to realize a 0 to 10v output swing. a dual ?2v to ?5v supply is required to realize a ?0v output swing, and allows unipolar, 0 to +10v output if uni/ bip is forced high. a +3v to +5v digital power supply and a +2.000v to +5.250v external reference voltage are also required. always bring up the reference voltage last. the other power supplies do not require sequencing. power-supply bypassing and ground management bypass v dd and v ss with 0.1? and 1.0? capacitors to agnd, and bypass v cc with 0.1? and 1.0? capacitors to dgnd. minimize trace lengths to reduce inductance. digital and ac transient signals on agnd or dgnd can create noise at the output. connect agnd and dgnd to the highest quality ground available. use proper ground- ing techniques, such as a multilayer board with a low- inductance ground plane or star connect all ground- return paths back to agnd. carefully lay out the traces between channels to reduce ac crosscoupling and crosstalk. wire-wrapped boards, sockets, and bread- boards are not recommended. MAX5312 10v, 12-bit, serial, voltage-output dac ______________________________________________________________________________________ 17 hex digital input code (lsb) -2048 -2047 -2046 -2045 +2047 +2046 +2045 +2044 +1 0 -1 analog output voltage (lsb) 001 000 002 003 7ff 800 801 ffc ffd fff ffe 4 x v ref 1 lsb = 4 x v ref 4096 figure 6. bipolar transfer function hex digital input code (lsb) 0 1 2 3 4095 4094 4093 4092 2049 2048 2047 analog output voltage (lsb) 001 000 002 003 7ff 800 801 ffc ffd fff ffe 2 x v ref 1 lsb = 2 x v ref 4096 figure 5. unipolar transfer function
MAX5312 10v, 12-bit, serial, voltage-output dac 18 ______________________________________________________________________________________ MAX5312 MAX5312 MAX5312 to other serial devices din sclk dout din sclk dout din sclk dout sclk din cs cs cs cs figure 7. daisy chaining devices chip information transistor count: 3280 technology: bicmos
MAX5312 10v, 12-bit, serial, voltage-output dac maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 19 2003 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) ssop.eps package outline, ssop, 5.3 mm 1 1 21-0056 c rev. document control no. approval proprietary information title: notes: 1. d&e do not include mold flash. 2. mold flash or protrusions not to exceed .15 mm (.006"). 3. controlling dimension: millimeters. 4. meets jedec mo150. 5. leads to be coplanar within 0.10 mm. 7.90 h l 0 0.301 0.025 8 0.311 0.037 0 7.65 0.63 8 0.95 max 5.38 millimeters b c d e e a1 dim a see variations 0.0256 bsc 0.010 0.004 0.205 0.002 0.015 0.008 0.212 0.008 inches min max 0.078 0.65 bsc 0.25 0.09 5.20 0.05 0.38 0.20 0.21 min 1.73 1.99 millimeters 6.07 6.07 10.07 8.07 7.07 inches d d d d d 0.239 0.239 0.397 0.317 0.278 min 0.249 0.249 0.407 0.328 0.289 max min 6.33 6.33 10.33 8.33 7.33 14l 16l 28l 24l 20l max n a d e a1 l c h e n 1 2 b 0.068

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